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diff --git a/bugs/yosys_7.md b/bugs/yosys_7.md new file mode 100644 index 0000000..c37d9b5 --- /dev/null +++ b/bugs/yosys_7.md @@ -0,0 +1,78 @@ +# Initial value of register ignored during synthesis + +[ [Issue 997](https://github.com/YosysHQ/yosys/issues/997) ] + +## Steps to reproduce the issue + +Consider the following verilog code. + +```verilog +module top (y, clk, wire4); + output wire [1:0] y; + input clk; + input signed wire4; + reg [1:0] reg10 = 0; + always @(posedge clk) begin + reg10 <= wire4; + end + assign y = reg10; +endmodule +``` + +When synthesised using + +``` +yosys -p 'read -formal rtl.v; synth; write_verilog -noattr syn_yosys.v' +``` + +and Yosys version + +``` +Generated by Yosys 0.8+450 (git sha1 09467bb9, clang 8.0.0 -fPIC -Os) +``` + +the initial value of the register seems to be ignored. Therefore, during simulation, the bit is undefined at first, and only behaves correctly after the first clock cycle. + +This does not seem to happen with the official 0.8 release of Yosys. In that release, the expected behavior is generated. + +## Expected behavior + +It is expected that the register is initialised with 0. This was generated using the 0.8 release of Yosys. + +```verilog +/* Generated by Yosys 0.8 (git sha1 b003446, clang 7.0.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fPIC -Os) */ + +module top_1(y, clk, wire4); + input clk; + wire [1:0] reg10; + input wire4; + output [1:0] y; + reg \reg10_reg[0] = 1'h0; // <----- + always @(posedge clk) + \reg10_reg[0] <= wire4; + assign reg10[0] = \reg10_reg[0] ; + assign reg10[1] = reg10[0]; + assign y = { reg10[0], reg10[0] }; +endmodule +``` + +## Actual behavior + +However, it actually gets initialised with `1'hx`. + +```verilog +/* Generated by Yosys 0.8+450 (git sha1 09467bb9, clang 8.0.0 -fPIC -Os) */ + +module top_1(y, clk, wire4); + input clk; + wire [1:0] reg10; + input wire4; + output [1:0] y; + reg \reg10_reg[0] = 1'hx; // <----- + always @(posedge clk) + \reg10_reg[0] <= wire4; + assign reg10[0] = \reg10_reg[0] ; + assign reg10[1] = reg10[0]; + assign y = { reg10[0], reg10[0] }; +endmodule +``` |