diff options
Diffstat (limited to 'data')
| -rw-r--r-- | data/README.md | 5 | ||||
| -rw-r--r-- | data/cells_cyclone_v.v | 58 | ||||
| -rw-r--r-- | data/cells_xilinx_7.v | 13 |
3 files changed, 17 insertions, 59 deletions
diff --git a/data/README.md b/data/README.md new file mode 100644 index 0000000..def3ad3 --- /dev/null +++ b/data/README.md @@ -0,0 +1,5 @@ +# Cells + +The implementation of the cells were initially taken from [VlogHammer +scripts](https://github.com/YosysHQ/VlogHammer/tree/master/testbench/scripts). Additions +were then implemented manually. diff --git a/data/cells_cyclone_v.v b/data/cells_cyclone_v.v index be465d8..5bcb32f 100644 --- a/data/cells_cyclone_v.v +++ b/data/cells_cyclone_v.v @@ -8,7 +8,7 @@ module cyclonev_lcell_comb ( ); input dataa, datab, datac, datad, datae, dataf, datag, cin, sharein; - output reg combout, sumout, cout, shareout; + output reg combout = 0, sumout = 0, cout = 0, shareout = 0; parameter lut_mask = 64'hFFFFFFFFFFFFFFFF; parameter shared_arith = "off"; @@ -63,25 +63,8 @@ module cyclonev_lcell_comb ( begin e0_mask = mask[15:0]; e1_mask = mask[31:16]; - begin - e0_lut = lut4(e0_mask, dataa, datab, datac, datad); - e1_lut = lut4(e1_mask, dataa, datab, datac, datad); - if (datae === 1'bX) // X propogation - begin - if (e0_lut == e1_lut) - begin - lut5 = e0_lut; - end - else - begin - lut5 = 1'bX; - end - end - else - begin - lut5 = (datae == 1'b1) ? e1_lut : e0_lut; - end - end + e0_lut = lut4(e0_mask, dataa, datab, datac, datad); + e1_lut = lut4(e1_mask, dataa, datab, datac, datad); end endfunction @@ -101,29 +84,7 @@ module cyclonev_lcell_comb ( begin f0_mask = mask[31:0]; f1_mask = mask[63:32]; - begin - lut6 = mask[{dataf, datae, datad, datac, datab, dataa}]; - if (lut6 === 1'bX) - begin - f0_lut = lut5(f0_mask, dataa, datab, datac, datad, datae); - f1_lut = lut5(f1_mask, dataa, datab, datac, datad, datae); - if (dataf === 1'bX) // X propogation - begin - if (f0_lut == f1_lut) - begin - lut6 = f0_lut; - end - else - begin - lut6 = 1'bX; - end - end - else - begin - lut6 = (dataf == 1'b1) ? f1_lut : f0_lut; - end - end - end + lut6 = mask[{dataf, datae, datad, datac, datab, dataa}]; end endfunction @@ -257,10 +218,15 @@ module dffeas (d, clk, ena, clrn, prn, aload, asdata, sclr, sload, devclrn, devp input devclrn; input devpor; - output reg q; + output reg q = 0; - always @(posedge clk) begin - q <= d; + always @(posedge clk or posedge aload) begin + if (aload == 1'b1) + q <= asdata; + else if (sload == 1'b1) + q <= asdata; + else + q <= d; end endmodule diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v index c757c2f..cc72893 100644 --- a/data/cells_xilinx_7.v +++ b/data/cells_xilinx_7.v @@ -971,19 +971,6 @@ module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1); end endmodule // BUFGCTRL -module BUFGDLL (O, I); - output O; - input I; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - wire clkin_int; - wire clk0_out, clk180_out, clk270_out, clk2x_out; - wire clk90_out, clkdv_out, locked_out; - CLKDLL clkdll_inst (.CLK0(clk0_out), .CLK180(clk180_out), .CLK270(clk270_out), .CLK2X(clk2x_out), .CLK90(clk90_out), .CLKDV(clkdv_out), .LOCKED(locked_out), .CLKFB(O), .CLKIN(clkin_int), .RST(1'b0)); - defparam clkdll_inst.DUTY_CYCLE_CORRECTION = DUTY_CYCLE_CORRECTION; - IBUFG ibufg_inst (.O(clkin_int), .I(I)); - BUFG bufg_inst (.O(O), .I(clk0_out)); -endmodule // BUFGDLL - module BUFG_LB ( CLKOUT, CLKIN |