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Diffstat (limited to 'src/Test/VeriFuzz/CodeGen.hs')
| -rw-r--r-- | src/Test/VeriFuzz/CodeGen.hs | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/CodeGen.hs b/src/Test/VeriFuzz/CodeGen.hs index 85f1d1c..755f52f 100644 --- a/src/Test/VeriFuzz/CodeGen.hs +++ b/src/Test/VeriFuzz/CodeGen.hs @@ -1,3 +1,16 @@ +{-| +Module : Test.VeriFuzz.CodeGen +Description : Code generation for Verilog AST. +Copyright : (c) Yann Herklotz Grave 2018 +License : GPL-3 +Maintainer : ymherklotz@gmail.com +Stability : experimental +Portability : POSIX + +This module generates the code from the Verilog AST defined in +"Test.VeriFuzz.VerilogAST". +-} + {-# LANGUAGE OverloadedStrings #-} module Test.VeriFuzz.CodeGen where @@ -9,14 +22,17 @@ import qualified Data.Text.IO as T import Test.VeriFuzz.Internal.Shared import Test.VeriFuzz.VerilogAST +-- | Convert the 'SourceText' type to 'Text' so that it can be rendered. genSourceText :: SourceText -> Text genSourceText source = fromList $ genDescription <$> source ^. getSourceText +-- | Generate the 'Description' to 'Text'. genDescription :: Description -> Text genDescription desc = genModuleDecl $ desc ^. getDescription +-- | Generate the 'ModuleDecl' for a module and convert it to 'Text'. genModuleDecl :: ModuleDecl -> Text genModuleDecl mod = "module " <> mod ^. moduleId . getIdentifier @@ -27,6 +43,7 @@ genModuleDecl mod = ports = sep ",\n" $ genPort <$> mod ^. modPorts modItems = fromList $ genModuleItem <$> mod ^. moduleItems +-- | Generate the 'Port' description. genPort :: Port -> Text genPort port = " " <> dir <> " " <> name @@ -34,14 +51,17 @@ genPort port = dir = genPortDir $ port ^. portDir name = port ^. portName . getIdentifier +-- | Convert the 'PortDir' type to 'Text'. genPortDir :: PortDir -> Text genPortDir Input = "input" genPortDir Output = "output" genPortDir InOut = "inout" +-- | Generate a 'ModuleItem'. genModuleItem :: ModuleItem -> Text genModuleItem (Assign assign) = genContAssign assign +-- | Generate the 'ContinuousAssignment' to 'Text'. genContAssign :: ContAssign -> Text genContAssign assign = " assign " <> name <> " = " <> expr <> ";\n" @@ -49,6 +69,7 @@ genContAssign assign = name = assign ^. contAssignNetLVal . getIdentifier expr = genExpr $ assign ^. contAssignExpr +-- | Generate 'Expression' to 'Text'. genExpr :: Expression -> Text genExpr (OpExpr exprRhs bin exprLhs) = genExpr exprRhs <> genBinaryOperator bin <> genExpr exprLhs @@ -56,6 +77,7 @@ genExpr (PrimExpr prim) = genPrimary prim genExpr _ = "TODO" +-- | Generate a 'PrimaryExpression' to 'Text'. genPrimary :: Primary -> Text genPrimary (PrimNum num) = neg <> sh (num ^. numSize) <> "'d" <> (sh . abs) n @@ -66,10 +88,12 @@ genPrimary (PrimNum num) = neg = if n <= 0 then "-" else "" genPrimary (PrimId ident) = ident ^. getIdentifier +-- | Convert 'BinaryOperator' to 'Text'. genBinaryOperator :: BinaryOperator -> Text genBinaryOperator BinAnd = " & " genBinaryOperator BinOr = " | " genBinaryOperator BinXor = " ^ " +-- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'. render :: Text -> IO () render = T.putStrLn |