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-rw-r--r--src/Test/VeriFuzz/Graph/ASTGen.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 2a82592..00ec88b 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -42,7 +42,7 @@ outputsC c =
genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
genPortsAST f c =
- (port . frNode <$> f c)
+ port . frNode <$> f c
where
port = Port Wire 1
@@ -50,7 +50,7 @@ genPortsAST f c =
-- assignment expressions.
genAssignExpr :: Gate -> [Node] -> Maybe Expr
genAssignExpr g [] = Nothing
-genAssignExpr g (n:[]) = Just . Id $ frNode n
+genAssignExpr g [n] = Just . Id $ frNode n
genAssignExpr g (n:ns) = BinOp wire op <$> genAssignExpr g ns
where
wire = Id $ frNode n