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-rw-r--r--src/Test/VeriFuzz/Graph/ASTGen.hs9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 97b6c1c..d3e6ea5 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -62,20 +62,17 @@ genContAssignAST c (n, g) = ContAssign name <$> genAssignExpr g nodes
name = frNode n
genAssignAST :: Circuit -> [ContAssign]
-genAssignAST c =
- catMaybes $ genContAssignAST c <$> nodes
+genAssignAST c = catMaybes $ genContAssignAST c <$> nodes
where
gr = getCircuit c
nodes = G.labNodes gr
genModuleDeclAST :: Circuit -> ModuleDecl
-genModuleDeclAST c =
- ModuleDecl id ports items
+genModuleDeclAST c = ModuleDecl id ports items
where
id = Identifier "gen_module"
ports = genPortsAST c
items = Assign <$> genAssignAST c
generateAST :: Circuit -> SourceText
-generateAST c =
- SourceText [Description $ genModuleDeclAST c]
+generateAST c = SourceText [Description $ genModuleDeclAST c]