diff options
Diffstat (limited to 'src/Test/VeriFuzz/Graph/ASTGen.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index f481c24..781bbb9 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -22,6 +22,11 @@ import Test.VeriFuzz.VerilogAST fromNode :: G.Node -> Identifier fromNode node = Identifier . T.pack $ "w" <> show node +fromGate :: Gate -> BinaryOperator +fromGate And = BinAnd +fromGate Or = BinOr +fromGate Xor = BinXor + filterGr :: (G.Graph gr) => gr n e -> (G.Node -> Bool) -> [G.Node] filterGr graph f = filter f $ G.nodes graph @@ -34,13 +39,26 @@ genPortsAST c = ((Port Input . fromNode) <$> inp) ++ ((Port Output) . fromNode < out = filterGr graph $ zero G.outdeg G.indeg graph = getCircuit c +genContAssignAST :: Circuit -> G.LNode Gate -> ContAssign +genContAssignAST c g = + where + gr = getCircuit c + nodes = pre gr $ fst g + +genAssignAST :: Circuit -> [ContAssign] +genAssignAST c = + nodes + where + gr = getCircuit c + nodes = G.labNodes gr + genModuleDeclAST :: Circuit -> ModuleDecl genModuleDeclAST c = ModuleDecl id ports items where id = Identifier "gen_module" ports = genPortsAST c - items = [] + items = Assign <$> genAssignAST c generateAST :: Circuit -> SourceText generateAST c = |