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Diffstat (limited to 'src/Test/VeriFuzz/Verilog.hs')
-rw-r--r-- | src/Test/VeriFuzz/Verilog.hs | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/Verilog.hs b/src/Test/VeriFuzz/Verilog.hs new file mode 100644 index 0000000..e910d4d --- /dev/null +++ b/src/Test/VeriFuzz/Verilog.hs @@ -0,0 +1,24 @@ +{-| +Module : Test.VeriFuzz.Verilog +Description : The main verilog module with the syntax and code generation. +Copyright : (c) Yann Herklotz Grave 2018 +License : GPL-3 +Maintainer : ymherklotz@gmail.com +Stability : experimental +Portability : POSIX + +The main verilog module with the syntax and code generation. +-} + +module Test.VeriFuzz.Verilog + ( -- * AST + module Test.VeriFuzz.Verilog.AST + -- * Code Generation + , module Test.VeriFuzz.Verilog.CodeGen + -- * Verilog mutations + , module Test.VeriFuzz.Verilog.Mutate + ) where + +import Test.VeriFuzz.Verilog.AST +import Test.VeriFuzz.Verilog.CodeGen +import Test.VeriFuzz.Verilog.Mutate |