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-rw-r--r--src/Test/VeriFuzz/Verilog/Helpers.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index 6712d32..d3bc689 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -18,10 +18,10 @@ import qualified Data.Text
import Test.VeriFuzz.Verilog.AST
regDecl :: Identifier -> ModItem
-regDecl = Decl . Port (Reg False) 1
+regDecl = Decl Nothing . Port (Reg False) 1
wireDecl :: Identifier -> ModItem
-wireDecl = Decl . Port (PortNet Wire) 1
+wireDecl = Decl Nothing . Port (PortNet Wire) 1
modConn :: Text -> ModConn
modConn = ModConn . PrimExpr . PrimId . Identifier