diff options
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Mutate.hs')
-rw-r--r-- | src/Test/VeriFuzz/Verilog/Mutate.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index 9175664..b22fc2c 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -84,7 +84,7 @@ nestUpTo i src = -- it to the body of the second module. It first has to make all the inputs into -- @reg@. -- --- >>> SrcShow $ instantiateMod mod main +-- >>> instantiateMod mod main -- module main; -- wire [4:0] y; -- reg [4:0] x; @@ -104,7 +104,7 @@ instantiateMod mod main = -- | Initialise all the inputs and outputs to a module. -- --- >>> SrcShow $ initMod mod +-- >>> initMod mod -- module m(y, x); -- output wire [4:0] y; -- input wire [4:0] x; |