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Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/Mutate.hs | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index 66e56a1..6731b65 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -21,7 +21,11 @@ import Test.VeriFuzz.Verilog.AST -- | Return if the 'Identifier' is in a 'ModDecl'. inPort :: Identifier -> ModDecl -> Bool -inPort id mod = any (\a -> a ^. portName == id) $ mod ^. modPorts +inPort id mod = inInput || inOutput + where + inInput = any (\a -> a ^. portName == id) $ mod ^. modInPorts + inOutput = fromMaybe False . safe head $ (==id) <$> + mod ^.. modOutPort . _Just . portName -- | Find the last assignment of a specific wire/reg to an expression, and -- returns that expression. |