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Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/Mutate.hs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index 6731b65..6993fef 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -82,3 +82,8 @@ nestUpTo i src = instantiateMod :: ModDecl -> ModDecl -> ModDecl instantiateMod mod main = main + +-- | Initialise all the inputs and outputs to a module. +initMod :: ModDecl -> ModDecl +initMod mod = + mod |