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Diffstat (limited to 'src/VeriFuzz/ASTGen.hs')
| -rw-r--r-- | src/VeriFuzz/ASTGen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs index 7c295e1..9360a88 100644 --- a/src/VeriFuzz/ASTGen.hs +++ b/src/VeriFuzz/ASTGen.hs @@ -75,5 +75,5 @@ genModuleDeclAST c = ModDecl i output ports $ combineAssigns yPort a a = genAssignAST c yPort = Port Wire False 90 "y" -generateAST :: Circuit -> VerilogSrc -generateAST c = VerilogSrc [Description $ genModuleDeclAST c] +generateAST :: Circuit -> Verilog +generateAST c = Verilog [Description $ genModuleDeclAST c] |