diff options
Diffstat (limited to 'src/VeriFuzz/Circuit/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Circuit/Gen.hs | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index 323d8bb..eb7cb97 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -3,7 +3,7 @@ Module : Verilog.Circuit.Gen Description : Generate verilog from circuit. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -15,11 +15,9 @@ module VeriFuzz.Circuit.Gen ) where -import Data.Graph.Inductive ( LNode - , Node - ) -import qualified Data.Graph.Inductive as G -import Data.Maybe ( catMaybes ) +import Data.Graph.Inductive (LNode, Node) +import qualified Data.Graph.Inductive as G +import Data.Maybe (catMaybes) import VeriFuzz.Circuit.Base import VeriFuzz.Circuit.Internal import VeriFuzz.Verilog.AST |