1 files changed, 8 insertions, 8 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
index eb7cb97..1c4dd37 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriFuzz/Circuit/Gen.hs
@@ -10,18 +10,18 @@ Portability : POSIX
 Generate verilog from circuit.
 -}
 
-module VeriFuzz.Circuit.Gen
+module VeriSmith.Circuit.Gen
     ( generateAST
     )
 where
 
-import           Data.Graph.Inductive      (LNode, Node)
-import qualified Data.Graph.Inductive      as G
-import           Data.Maybe                (catMaybes)
-import           VeriFuzz.Circuit.Base
-import           VeriFuzz.Circuit.Internal
-import           VeriFuzz.Verilog.AST
-import           VeriFuzz.Verilog.Mutate
+import           Data.Graph.Inductive       (LNode, Node)
+import qualified Data.Graph.Inductive       as G
+import           Data.Maybe                 (catMaybes)
+import           VeriSmith.Circuit.Base
+import           VeriSmith.Circuit.Internal
+import           VeriSmith.Verilog.AST
+import           VeriSmith.Verilog.Mutate
 
 -- | Converts a 'CNode' to an 'Identifier'.
 frNode :: Node -> Identifier