diff options
Diffstat (limited to 'src/VeriFuzz/Circuit')
| -rw-r--r-- | src/VeriFuzz/Circuit/Gen.hs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index 817d2f8..1e31e56 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -38,7 +38,7 @@ inputsC :: Circuit -> [Node] inputsC c = inputs (getCircuit c) genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port] -genPortsAST f c = port . frNode <$> f c where port = Port Wire False 4 +genPortsAST f c = port . frNode <$> f c where port = Port Wire False 0 4 -- | Generates the nested expression AST, so that it can then generate the -- assignment expressions. @@ -67,13 +67,13 @@ genAssignAST c = catMaybes $ genContAssignAST c <$> nodes nodes = G.labNodes gr genModuleDeclAST :: Circuit -> ModDecl -genModuleDeclAST c = ModDecl i output ports $ combineAssigns yPort a +genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) [] where i = Identifier "gen_module" ports = genPortsAST inputsC c output = [] a = genAssignAST c - yPort = Port Wire False 90 "y" + yPort = Port Wire False 0 90 "y" generateAST :: Circuit -> Verilog -generateAST c = Verilog [Description $ genModuleDeclAST c] +generateAST c = Verilog [genModuleDeclAST c] |