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-rw-r--r--src/VeriFuzz/Gen.hs6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/VeriFuzz/Gen.hs b/src/VeriFuzz/Gen.hs
index b9545a8..6bc01c9 100644
--- a/src/VeriFuzz/Gen.hs
+++ b/src/VeriFuzz/Gen.hs
@@ -75,7 +75,7 @@ fromGraph = do
$ initMod
. head
$ nestUpTo 5 (generateAST gr)
- ^.. getVerilogSrc
+ ^.. getVerilog
. traverse
. getDescription
@@ -206,8 +206,8 @@ moduleDef top = do
-- | Procedural generation method for random Verilog. Uses internal 'Reader' and
-- 'State' to keep track of the current Verilog code structure.
-procedural :: Config -> Gen VerilogSrc
-procedural config = VerilogSrc . (: []) . Description <$> Hog.resize
+procedural :: Config -> Gen Verilog
+procedural config = Verilog . (: []) . Description <$> Hog.resize
num
(runReaderT (evalStateT (moduleDef True) context) config)
where