diff options
Diffstat (limited to 'src/VeriFuzz/Graph/ASTGen.hs')
| -rw-r--r-- | src/VeriFuzz/Graph/ASTGen.hs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/VeriFuzz/Graph/ASTGen.hs b/src/VeriFuzz/Graph/ASTGen.hs index 0403f51..ad7dd50 100644 --- a/src/VeriFuzz/Graph/ASTGen.hs +++ b/src/VeriFuzz/Graph/ASTGen.hs @@ -75,8 +75,7 @@ genModuleDeclAST c = ModDecl i output ports items i = Identifier "gen_module" ports = genPortsAST inputsC c output = [Port Wire 90 "y"] - items = - genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] + items = genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] generateAST :: Circuit -> VerilogSrc generateAST c = VerilogSrc [Description $ genModuleDeclAST c] |