3 files changed, 3 insertions, 6 deletions
diff --git a/src/VeriFuzz/Graph/ASTGen.hs b/src/VeriFuzz/Graph/ASTGen.hs
index 0403f51..ad7dd50 100644
--- a/src/VeriFuzz/Graph/ASTGen.hs
+++ b/src/VeriFuzz/Graph/ASTGen.hs
@@ -75,8 +75,7 @@ genModuleDeclAST c = ModDecl i output ports items
   i      = Identifier "gen_module"
   ports  = genPortsAST inputsC c
   output = [Port Wire 90 "y"]
-  items =
-    genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports]
+  items  = genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports]
 
 generateAST :: Circuit -> VerilogSrc
 generateAST c = VerilogSrc [Description $ genModuleDeclAST c]
diff --git a/src/VeriFuzz/Graph/CodeGen.hs b/src/VeriFuzz/Graph/CodeGen.hs
index 3c45a9c..56b28aa 100644
--- a/src/VeriFuzz/Graph/CodeGen.hs
+++ b/src/VeriFuzz/Graph/CodeGen.hs
@@ -35,8 +35,7 @@ toOperator Or  = " | "
 toOperator Xor = " ^ "
 
 statList :: Gate -> [Node] -> Maybe Text
-statList g n = toStr <$> safe tail n
-  where toStr = fold . fmap ((<> toOperator g) . fromNode)
+statList g n = toStr <$> safe tail n where toStr = fold . fmap ((<> toOperator g) . fromNode)
 
 lastEl :: [Node] -> Maybe Text
 lastEl n = fromNode <$> safe head n
diff --git a/src/VeriFuzz/Graph/Random.hs b/src/VeriFuzz/Graph/Random.hs
index 5b36c48..573c179 100644
--- a/src/VeriFuzz/Graph/Random.hs
+++ b/src/VeriFuzz/Graph/Random.hs
@@ -25,8 +25,7 @@ import           Test.QuickCheck                ( Arbitrary
 import qualified Test.QuickCheck               as QC
 
 dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b]
-dupFolder cont ns = unique cont : ns
-  where unique (a, b, c, d) = (nub a, b, c, nub d)
+dupFolder cont ns = unique cont : ns where unique (a, b, c, d) = (nub a, b, c, nub d)
 
 -- | Remove duplicates.
 rDups :: (Eq a, Eq b) => Gr a b -> Gr a b