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-rw-r--r--src/VeriFuzz/Internal/AST.hs6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/VeriFuzz/Internal/AST.hs b/src/VeriFuzz/Internal/AST.hs
index 16d40a3..49e1d30 100644
--- a/src/VeriFuzz/Internal/AST.hs
+++ b/src/VeriFuzz/Internal/AST.hs
@@ -34,8 +34,8 @@ setModName str = modId .~ Identifier str
addModPort :: Port -> ModDecl -> ModDecl
addModPort port = modInPorts %~ (:) port
-addDescription :: Description -> VerilogSrc -> VerilogSrc
-addDescription desc = getVerilogSrc %~ (:) desc
+addDescription :: Description -> Verilog -> Verilog
+addDescription desc = getVerilog %~ (:) desc
testBench :: ModDecl
testBench = ModDecl
@@ -61,7 +61,7 @@ testBench = ModDecl
]
]
-addTestBench :: VerilogSrc -> VerilogSrc
+addTestBench :: Verilog -> Verilog
addTestBench = addDescription $ Description testBench
defaultPort :: Identifier -> Port