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Diffstat (limited to 'src/VeriFuzz/Sim/Template.hs')
-rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 5226106..bd58b83 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -16,6 +16,7 @@ module VeriFuzz.Sim.Template ( yosysSatConfig , yosysSimConfig , xstSynthConfig + , vivadoSynthConfig , sbyConfig ) where @@ -74,6 +75,17 @@ xstSynthConfig top = [st|run |] -- brittany-disable-next-binding +vivadoSynthConfig :: Text -> Text -> Text +vivadoSynthConfig top outf = [st| +# CRITICAL WARNING: [Synth 8-5821] Potential divide by zero +set_msg_config -id {Synth 8-5821} -new_severity {WARNING} + +read_verilog rtl.v +synth_design -part xc7k70t -top #{top} +write_verilog -force #{outf} +|] + +-- brittany-disable-next-binding sbyConfig :: (Tool a, Tool b) => FilePath -> a -> Maybe b -> SourceInfo -> Text sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options] mode prove |