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-rw-r--r--src/VeriFuzz/Sim/XST.hs8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 324f227..92dcaa1 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -55,9 +55,9 @@ runSynthXST sim (SourceInfo top src) = do
writefile xstFile $ xstSynthConfig top
writefile prjFile [st|verilog work "rtl.v"|]
writefile "rtl.v" $ genSource src
- echoP "XST: run"
+ logger "XST: run"
exec (xstPath sim) ["-ifn", toTextIgnore xstFile]
- liftSh $ echoP "XST: netgen"
+ liftSh $ logger "XST: netgen"
exec
(netgenPath sim)
[ "-w"
@@ -67,14 +67,14 @@ runSynthXST sim (SourceInfo top src) = do
, toTextIgnore $ synthOutput sim
]
liftSh $ do
- echoP "XST: clean"
+ logger "XST: clean"
noPrint $ run_
"sed"
[ "-i"
, "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;"
, toTextIgnore $ synthOutput sim
]
- echoP "XST: done"
+ logger "XST: done"
where
modFile = fromText top
xstFile = modFile <.> "xst"