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-rw-r--r--src/VeriFuzz/Sim/XST.hs5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 488c404..b5b1b8b 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -29,6 +29,7 @@ import VeriFuzz.Verilog.CodeGen
data XST = XST { xstPath :: {-# UNPACK #-} !FilePath
, netgenPath :: {-# UNPACK #-} !FilePath
+ , xstOutput :: {-# UNPACK #-} !FilePath
}
deriving (Eq)
@@ -40,9 +41,11 @@ instance Tool XST where
instance Synthesiser XST where
runSynth = runSynthXST
+ synthOutput = xstOutput
+ setSynthOutput (XST a b _) f = XST a b f
defaultXST :: XST
-defaultXST = XST "xst" "netgen"
+defaultXST = XST "xst" "netgen" "xst/syn_xst.v"
runSynthXST :: XST -> SourceInfo -> FilePath -> ResultSh ()
runSynthXST sim (SourceInfo top src) outf = do