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-rw-r--r--src/VeriFuzz/Sim/XST.hs12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 359b587..9019db8 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -28,13 +28,13 @@ import VeriFuzz.Verilog.CodeGen
data XST = XST { xstPath :: {-# UNPACK #-} !FilePath
, netgenPath :: {-# UNPACK #-} !FilePath
}
- deriving (Eq, Show)
+ deriving (Eq, Show)
instance Tool XST where
- toText _ = "xst"
+ toText _ = "xst"
instance Synthesisor XST where
- runSynth = runSynthXST
+ runSynth = runSynthXST
defaultXST :: XST
defaultXST = XST "xst" "netgen"
@@ -46,9 +46,9 @@ runSynthXST sim (SourceInfo top src) outf = do
writefile prjFile [st|verilog work "rtl.v"|]
writefile "rtl.v" $ genSource src
echoP "XST: run"
- _ <- logger dir "xst" $ timeout (xstPath sim) ["-ifn", toTextIgnore xstFile]
+ logger_ dir "xst" $ timeout (xstPath sim) ["-ifn", toTextIgnore xstFile]
echoP "XST: netgen"
- _ <- logger dir "netgen" $ run
+ logger_ dir "netgen" $ run
(netgenPath sim)
[ "-w"
, "-ofmt"
@@ -65,6 +65,6 @@ runSynthXST sim (SourceInfo top src) outf = do
]
echoP "XST: done"
where
- modFile = fromText top
+ modFile = "xst_" <> fromText top
xstFile = modFile <.> "xst"
prjFile = modFile <.> "prj"