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-rw-r--r--src/VeriFuzz/Sim/Yosys.hs6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 3729a1e..02a00d5 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -67,7 +67,11 @@ runSynthYosys sim (SourceInfo _ src) = do
dir' <- pwd
writefile inpf $ genSource src
return dir'
- execute_ SynthFail dir "yosys" (yosysPath sim)
+ execute_
+ SynthFail
+ dir
+ "yosys"
+ (yosysPath sim)
[ "-p"
, "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out
]