diff options
Diffstat (limited to 'src/VeriFuzz/Sim')
| -rw-r--r-- | src/VeriFuzz/Sim/Quartus.hs | 7 | ||||
| -rw-r--r-- | src/VeriFuzz/Sim/Vivado.hs | 7 | ||||
| -rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 6 |
3 files changed, 17 insertions, 3 deletions
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs index a099495..4217abb 100644 --- a/src/VeriFuzz/Sim/Quartus.hs +++ b/src/VeriFuzz/Sim/Quartus.hs @@ -53,7 +53,12 @@ runSynthQuartus sim (SourceInfo top src) = do dir <- liftSh pwd let ex = execute_ SynthFail dir "quartus" liftSh . writefile inpf $ genSource src - liftSh . noPrint $ run_ "sed" ["-i", "s/^module/(* multstyle = \"logic\" *) module/;", toTextIgnore inpf] + liftSh . noPrint $ run_ + "sed" + [ "-i" + , "s/^module/(* multstyle = \"logic\" *) module/;" + , toTextIgnore inpf + ] ex (exec "quartus_map") [top, "--source=" <> toTextIgnore inpf, "--family=Cyclone V"] ex (exec "quartus_fit") [top, "--part=5CGXFC7D6F31C6"] diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs index 90eed2d..a4feb07 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/VeriFuzz/Sim/Vivado.hs @@ -56,7 +56,12 @@ runSynthVivado sim (SourceInfo top src) = do writefile vivadoTcl . vivadoSynthConfig top . toTextIgnore $ synthOutput sim writefile "rtl.v" $ genSource src - run_ "sed" ["s/^module/(* use_dsp48=\"no\" *) (* use_dsp=\"no\" *) module/;", "-i", "rtl.v"] + run_ + "sed" + [ "s/^module/(* use_dsp48=\"no\" *) (* use_dsp=\"no\" *) module/;" + , "-i" + , "rtl.v" + ] let exec_ n = execute_ SynthFail dir diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 3729a1e..02a00d5 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -67,7 +67,11 @@ runSynthYosys sim (SourceInfo _ src) = do dir' <- pwd writefile inpf $ genSource src return dir' - execute_ SynthFail dir "yosys" (yosysPath sim) + execute_ + SynthFail + dir + "yosys" + (yosysPath sim) [ "-p" , "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out ] |