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-rw-r--r--src/VeriFuzz/Sim/Icarus.hs56
-rw-r--r--src/VeriFuzz/Sim/Identity.hs20
-rw-r--r--src/VeriFuzz/Sim/Internal.hs16
-rw-r--r--src/VeriFuzz/Sim/Quartus.hs18
-rw-r--r--src/VeriFuzz/Sim/Template.hs20
-rw-r--r--src/VeriFuzz/Sim/Vivado.hs20
-rw-r--r--src/VeriFuzz/Sim/XST.hs22
-rw-r--r--src/VeriFuzz/Sim/Yosys.hs28
8 files changed, 100 insertions, 100 deletions
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index e7c92dc..f104630 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.Icarus
+Module : VeriSmith.Sim.Icarus
Description : Icarus verilog module.
Copyright : (c) 2018-2019, Yann Herklotz
License : BSD-3
@@ -10,42 +10,42 @@ Portability : POSIX
Icarus verilog module.
-}
-module VeriFuzz.Sim.Icarus
+module VeriSmith.Sim.Icarus
( Icarus(..)
, defaultIcarus
, runSimIc
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
+import Control.DeepSeq (NFData, rnf, rwhnf)
import Control.Lens
-import Control.Monad (void)
-import Crypto.Hash (Digest, hash)
-import Crypto.Hash.Algorithms (SHA256)
-import Data.Binary (encode)
+import Control.Monad (void)
+import Crypto.Hash (Digest, hash)
+import Crypto.Hash.Algorithms (SHA256)
+import Data.Binary (encode)
import Data.Bits
-import qualified Data.ByteArray as BA (convert)
-import Data.ByteString (ByteString)
-import qualified Data.ByteString as B
-import Data.ByteString.Lazy (toStrict)
-import qualified Data.ByteString.Lazy as L (ByteString)
-import Data.Char (digitToInt)
-import Data.Foldable (fold)
-import Data.List (transpose)
-import Data.Maybe (listToMaybe)
-import Data.Text (Text)
-import qualified Data.Text as T
-import Numeric (readInt)
-import Prelude hiding (FilePath)
+import qualified Data.ByteArray as BA (convert)
+import Data.ByteString (ByteString)
+import qualified Data.ByteString as B
+import Data.ByteString.Lazy (toStrict)
+import qualified Data.ByteString.Lazy as L (ByteString)
+import Data.Char (digitToInt)
+import Data.Foldable (fold)
+import Data.List (transpose)
+import Data.Maybe (listToMaybe)
+import Data.Text (Text)
+import qualified Data.Text as T
+import Numeric (readInt)
+import Prelude hiding (FilePath)
import Shelly
-import Shelly.Lifted (liftSh)
-import VeriFuzz.Sim.Internal
-import VeriFuzz.Sim.Template
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.BitVec
-import VeriFuzz.Verilog.CodeGen
-import VeriFuzz.Verilog.Internal
-import VeriFuzz.Verilog.Mutate
+import Shelly.Lifted (liftSh)
+import VeriSmith.Sim.Internal
+import VeriSmith.Sim.Template
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.BitVec
+import VeriSmith.Verilog.CodeGen
+import VeriSmith.Verilog.Internal
+import VeriSmith.Verilog.Mutate
data Icarus = Icarus { icarusPath :: FilePath
, vvpPath :: FilePath
diff --git a/src/VeriFuzz/Sim/Identity.hs b/src/VeriFuzz/Sim/Identity.hs
index bfa99f5..cac230f 100644
--- a/src/VeriFuzz/Sim/Identity.hs
+++ b/src/VeriFuzz/Sim/Identity.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.Identity
+Module : VeriSmith.Sim.Identity
Description : The identity simulator and synthesiser.
Copyright : (c) 2019, Yann Herklotz Grave
License : GPL-3
@@ -10,20 +10,20 @@ Portability : POSIX
The identity simulator and synthesiser.
-}
-module VeriFuzz.Sim.Identity
+module VeriSmith.Sim.Identity
( Identity(..)
, defaultIdentity
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
-import Shelly (FilePath)
-import Shelly.Lifted (writefile)
-import VeriFuzz.Sim.Internal
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
+import Control.DeepSeq (NFData, rnf, rwhnf)
+import Data.Text (Text, unpack)
+import Prelude hiding (FilePath)
+import Shelly (FilePath)
+import Shelly.Lifted (writefile)
+import VeriSmith.Sim.Internal
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.CodeGen
data Identity = Identity { identityDesc :: {-# UNPACK #-} !Text
, identityOutput :: {-# UNPACK #-} !FilePath
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index f5351c7..017faad 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.Internal
+Module : VeriSmith.Sim.Internal
Description : Class of the simulator.
Copyright : (c) 2018-2019, Yann Herklotz
License : BSD-3
@@ -12,7 +12,7 @@ Class of the simulator and the synthesize tool.
{-# LANGUAGE DeriveFunctor #-}
-module VeriFuzz.Sim.Internal
+module VeriSmith.Sim.Internal
( ResultSh
, resultSh
, Tool(..)
@@ -54,9 +54,9 @@ import Prelude hiding (FilePath)
import Shelly
import Shelly.Lifted (MonadSh, liftSh)
import System.FilePath.Posix (takeBaseName)
-import VeriFuzz.Internal
-import VeriFuzz.Result
-import VeriFuzz.Verilog.AST
+import VeriSmith.Internal
+import VeriSmith.Result
+import VeriSmith.Verilog.AST
-- | Tool class.
class Tool a where
@@ -100,7 +100,7 @@ renameSource :: (Synthesiser a) => a -> SourceInfo -> SourceInfo
renameSource a src =
src & infoSrc . _Wrapped . traverse . modId . _Wrapped %~ (<> toText a)
--- | Type synonym for a 'ResultT' that will be used throughout 'VeriFuzz'. This
+-- | Type synonym for a 'ResultT' that will be used throughout 'VeriSmith'. This
-- has instances for 'MonadSh' and 'MonadIO' if the 'Monad' it is parametrised
-- with also has those instances.
type ResultSh = ResultT Failed Sh
@@ -146,7 +146,7 @@ replaceMods fp t (SourceInfo _ src) =
rootPath :: Sh FilePath
rootPath = do
current <- pwd
- maybe current fromText <$> get_env "VERIFUZZ_ROOT"
+ maybe current fromText <$> get_env "VERISMITH_ROOT"
timeout :: FilePath -> [Text] -> Sh Text
timeout = command1 "timeout" ["300"] . toTextIgnore
@@ -170,7 +170,7 @@ logger t = do
fn <- pwd
currentTime <- liftIO getZonedTime
echo
- $ "VeriFuzz "
+ $ "VeriSmith "
<> T.pack (formatTime defaultTimeLocale "%H:%M:%S " currentTime)
<> bname fn
<> " - "
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index 254bfa5..6837133 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.Quartus
+Module : VeriSmith.Sim.Quartus
Description : Quartus synthesiser implementation.
Copyright : (c) 2019, Yann Herklotz Grave
License : GPL-3
@@ -10,20 +10,20 @@ Portability : POSIX
Quartus synthesiser implementation.
-}
-module VeriFuzz.Sim.Quartus
+module VeriSmith.Sim.Quartus
( Quartus(..)
, defaultQuartus
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.DeepSeq (NFData, rnf, rwhnf)
+import Data.Text (Text, unpack)
+import Prelude hiding (FilePath)
import Shelly
-import Shelly.Lifted (liftSh)
-import VeriFuzz.Sim.Internal
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
+import Shelly.Lifted (liftSh)
+import VeriSmith.Sim.Internal
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.CodeGen
data Quartus = Quartus { quartusBin :: !(Maybe FilePath)
, quartusDesc :: {-# UNPACK #-} !Text
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 9b8ee9f..d232420 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.Template
+Module : VeriSmith.Sim.Template
Description : Template file for different configuration files
Copyright : (c) 2019, Yann Herklotz
License : GPL-3
@@ -12,7 +12,7 @@ Template file for different configuration files.
{-# LANGUAGE QuasiQuotes #-}
-module VeriFuzz.Sim.Template
+module VeriSmith.Sim.Template
( yosysSatConfig
, yosysSimConfig
, xstSynthConfig
@@ -22,15 +22,15 @@ module VeriFuzz.Sim.Template
)
where
-import Control.Lens ((^..))
-import Data.Text (Text)
-import qualified Data.Text as T
-import Prelude hiding (FilePath)
+import Control.Lens ((^..))
+import Data.Text (Text)
+import qualified Data.Text as T
+import Prelude hiding (FilePath)
import Shelly
-import Text.Shakespeare.Text (st)
-import VeriFuzz.Sim.Internal
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
+import Text.Shakespeare.Text (st)
+import VeriSmith.Sim.Internal
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.CodeGen
rename :: Text -> [Text] -> Text
rename end entries =
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index 4ddb048..e8d8f0d 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.Vivado
+Module : VeriSmith.Sim.Vivado
Description : Vivado Synthesiser implementation.
Copyright : (c) 2019, Yann Herklotz Grave
License : GPL-3
@@ -10,21 +10,21 @@ Portability : POSIX
Vivado Synthesiser implementation.
-}
-module VeriFuzz.Sim.Vivado
+module VeriSmith.Sim.Vivado
( Vivado(..)
, defaultVivado
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.DeepSeq (NFData, rnf, rwhnf)
+import Data.Text (Text, unpack)
+import Prelude hiding (FilePath)
import Shelly
-import Shelly.Lifted (liftSh)
-import VeriFuzz.Sim.Internal
-import VeriFuzz.Sim.Template
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
+import Shelly.Lifted (liftSh)
+import VeriSmith.Sim.Internal
+import VeriSmith.Sim.Template
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.CodeGen
data Vivado = Vivado { vivadoBin :: !(Maybe FilePath)
, vivadoDesc :: {-# UNPACK #-} !Text
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 86db667..30a4b0b 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.XST
+Module : VeriSmith.Sim.XST
Description : XST (ise) simulator implementation.
Copyright : (c) 2018-2019, Yann Herklotz
License : BSD-3
@@ -12,22 +12,22 @@ XST (ise) simulator implementation.
{-# LANGUAGE QuasiQuotes #-}
-module VeriFuzz.Sim.XST
+module VeriSmith.Sim.XST
( XST(..)
, defaultXST
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.DeepSeq (NFData, rnf, rwhnf)
+import Data.Text (Text, unpack)
+import Prelude hiding (FilePath)
import Shelly
-import Shelly.Lifted (liftSh)
-import Text.Shakespeare.Text (st)
-import VeriFuzz.Sim.Internal
-import VeriFuzz.Sim.Template
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
+import Shelly.Lifted (liftSh)
+import Text.Shakespeare.Text (st)
+import VeriSmith.Sim.Internal
+import VeriSmith.Sim.Template
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.CodeGen
data XST = XST { xstBin :: !(Maybe FilePath)
, xstDesc :: {-# UNPACK #-} !Text
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 8c73b86..1f583a8 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Sim.Yosys
+Module : VeriSmith.Sim.Yosys
Description : Yosys simulator implementation.
Copyright : (c) 2018-2019, Yann Herklotz
License : BSD-3
@@ -12,7 +12,7 @@ Yosys simulator implementation.
{-# LANGUAGE QuasiQuotes #-}
-module VeriFuzz.Sim.Yosys
+module VeriSmith.Sim.Yosys
( Yosys(..)
, defaultYosys
, runEquiv
@@ -20,20 +20,20 @@ module VeriFuzz.Sim.Yosys
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
+import Control.DeepSeq (NFData, rnf, rwhnf)
import Control.Lens
-import Control.Monad (void)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.Monad (void)
+import Data.Text (Text, unpack)
+import Prelude hiding (FilePath)
import Shelly
-import Shelly.Lifted (liftSh)
-import Text.Shakespeare.Text (st)
-import VeriFuzz.Result
-import VeriFuzz.Sim.Internal
-import VeriFuzz.Sim.Template
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
-import VeriFuzz.Verilog.Mutate
+import Shelly.Lifted (liftSh)
+import Text.Shakespeare.Text (st)
+import VeriSmith.Result
+import VeriSmith.Sim.Internal
+import VeriSmith.Sim.Template
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.CodeGen
+import VeriSmith.Verilog.Mutate
data Yosys = Yosys { yosysBin :: !(Maybe FilePath)
, yosysDesc :: {-# UNPACK #-} !Text
generated by cgit (git 2.34.1) at 2024-06-26 15:14:02 +0000