diff options
Diffstat (limited to 'src/VeriFuzz/Sim')
-rw-r--r-- | src/VeriFuzz/Sim/Icarus.hs | 3 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Internal.hs | 6 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Reduce.hs | 4 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 2 |
4 files changed, 8 insertions, 7 deletions
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs index 14023b7..8876706 100644 --- a/src/VeriFuzz/Sim/Icarus.hs +++ b/src/VeriFuzz/Sim/Icarus.hs @@ -93,8 +93,9 @@ runSimIcarus sim rinfo bss = do $ fold (addDisplay $ assignFunc (_modInPorts m) <$> bss) <> (SysTaskEnable $ Task "finish" []) ] + [] let newtb = instantiateMod m tb - let modWithTb = Verilog $ Description <$> [newtb, m] + let modWithTb = Verilog [newtb, m] writefile "main.v" $ genSource modWithTb runSimWithFile sim "main.v" bss where m = rinfo ^. mainModule diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs index 062035c..145042a 100644 --- a/src/VeriFuzz/Sim/Internal.hs +++ b/src/VeriFuzz/Sim/Internal.hs @@ -73,10 +73,10 @@ mainModule = lens get_ set_ where set_ (SourceInfo top main) v = SourceInfo top (main & getModule %~ update top v) - update top v m@(ModDecl (Identifier i) _ _ _) | i == top = v - | otherwise = m + update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v + | otherwise = m get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule - f top (ModDecl (Identifier i) _ _ _) = i == top + f top (ModDecl (Identifier i) _ _ _ _) = i == top rootPath :: Sh FilePath rootPath = do diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs index 5684ed5..361df3e 100644 --- a/src/VeriFuzz/Sim/Reduce.hs +++ b/src/VeriFuzz/Sim/Reduce.hs @@ -67,8 +67,8 @@ filterExpr ids (Id i) = if i `notElem` ids then Number 1 0 else Id i filterExpr _ e = e filterDecl :: [Identifier] -> ModItem -> Bool -filterDecl ids (Decl Nothing (Port _ _ _ i)) = i `elem` ids -filterDecl _ _ = True +filterDecl ids (Decl Nothing (Port _ _ _ _ i) _) = i `elem` ids +filterDecl _ _ = True filterAssigns :: [Port] -> ModItem -> Bool filterAssigns out (ModCA (ContAssign i _)) = diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 0fc74a0..f630ea6 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -91,7 +91,7 @@ sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options] mode prove [engines] -smtbmc +smtbmc z3 [script] #{readL} |