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-rw-r--r--src/VeriFuzz/Simulator/Xst.hs8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs
index 415a45e..03c1707 100644
--- a/src/VeriFuzz/Simulator/Xst.hs
+++ b/src/VeriFuzz/Simulator/Xst.hs
@@ -42,10 +42,10 @@ runSynthXst sim m outf = do
writefile xstFile $ xstSynthConfig m
writefile prjFile [st|verilog work "rtl.v"|]
writefile "rtl.v" $ genSource m
- timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
- run_ (netgenPath sim)
- ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
- run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
+ noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
+ noPrint $ run_ (netgenPath sim)
+ ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
+ noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
where
modFile = fromText $ modName m
xstFile = modFile <.> "xst"