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-rw-r--r--src/VeriFuzz/Simulator/Xst.hs12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs
index 2314dd1..415a45e 100644
--- a/src/VeriFuzz/Simulator/Xst.hs
+++ b/src/VeriFuzz/Simulator/Xst.hs
@@ -37,16 +37,16 @@ defaultXst :: Xst
defaultXst =
Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen"
--- brittany-disable-next-binding
runSynthXst :: Xst -> ModDecl -> FilePath -> Sh ()
runSynthXst sim m outf = do
writefile xstFile $ xstSynthConfig m
writefile prjFile [st|verilog work "rtl.v"|]
writefile "rtl.v" $ genSource m
timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
- run_ (netgenPath sim) ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
+ run_ (netgenPath sim)
+ ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
- where
- modFile = fromText $ modName m
- xstFile = modFile <.> "xst"
- prjFile = modFile <.> "prj"
+ where
+ modFile = fromText $ modName m
+ xstFile = modFile <.> "xst"
+ prjFile = modFile <.> "prj"