4 files changed, 23 insertions, 21 deletions
diff --git a/src/VeriFuzz/Simulator/General.hs b/src/VeriFuzz/Simulator/General.hs
index 9001bf9..3615d3a 100644
--- a/src/VeriFuzz/Simulator/General.hs
+++ b/src/VeriFuzz/Simulator/General.hs
@@ -12,11 +12,11 @@ Class of the simulator and the synthesize tool.
 
 module VeriFuzz.Simulator.General where
 
-import           Data.Bits                      ( shiftL )
-import           Data.ByteString                ( ByteString )
-import qualified Data.ByteString               as B
-import           Data.Text                      ( Text )
-import           Prelude                 hiding ( FilePath )
+import           Data.Bits            (shiftL)
+import           Data.ByteString      (ByteString)
+import qualified Data.ByteString      as B
+import           Data.Text            (Text)
+import           Prelude              hiding (FilePath)
 import           Shelly
 import           VeriFuzz.Verilog.AST
 
diff --git a/src/VeriFuzz/Simulator/Icarus.hs b/src/VeriFuzz/Simulator/Icarus.hs
index fdb1ad6..4782585 100644
--- a/src/VeriFuzz/Simulator/Icarus.hs
+++ b/src/VeriFuzz/Simulator/Icarus.hs
@@ -13,12 +13,12 @@ Icarus verilog module.
 module VeriFuzz.Simulator.Icarus where
 
 import           Control.Lens
-import           Data.ByteString                ( ByteString )
-import qualified Data.ByteString               as B
-import           Data.Foldable                  ( fold )
+import           Data.ByteString            (ByteString)
+import qualified Data.ByteString            as B
+import           Data.Foldable              (fold)
 import           Data.Hashable
-import           Data.List                      ( transpose )
-import           Prelude                 hiding ( FilePath )
+import           Data.List                  (transpose)
+import           Prelude                    hiding (FilePath)
 import           Shelly
 import           VeriFuzz.Simulator.General
 import           VeriFuzz.Verilog
diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs
index 1a0763c..29d1e4a 100644
--- a/src/VeriFuzz/Simulator/Xst.hs
+++ b/src/VeriFuzz/Simulator/Xst.hs
@@ -14,10 +14,10 @@ Xst (ise) simulator implementation.
 
 module VeriFuzz.Simulator.Xst where
 
-import           Control.Lens            hiding ( (<.>) )
-import           Prelude                 hiding ( FilePath )
+import           Control.Lens               hiding ((<.>))
+import           Prelude                    hiding (FilePath)
 import           Shelly
-import           Text.Shakespeare.Text          ( st )
+import           Text.Shakespeare.Text      (st)
 import           VeriFuzz.Simulator.General
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
diff --git a/src/VeriFuzz/Simulator/Yosys.hs b/src/VeriFuzz/Simulator/Yosys.hs
index 028fbb2..8f40ea9 100644
--- a/src/VeriFuzz/Simulator/Yosys.hs
+++ b/src/VeriFuzz/Simulator/Yosys.hs
@@ -15,10 +15,10 @@ Yosys simulator implementation.
 module VeriFuzz.Simulator.Yosys where
 
 import           Control.Lens
-import           Data.Text                      ( Text )
-import           Prelude                 hiding ( FilePath )
+import           Data.Text                  (Text)
+import           Prelude                    hiding (FilePath)
 import           Shelly
-import           Text.Shakespeare.Text          ( st )
+import           Text.Shakespeare.Text      (st)
 import           VeriFuzz.Simulator.General
 import           VeriFuzz.Verilog
 
@@ -71,12 +71,10 @@ sat -timeout 20 -verify-no-timeout -ignore_div_by_zero -prove y_1 y_2 #{modName}
     modName = m ^. moduleId . getIdentifier
     -- ids = T.intercalate "," $ allVars m ^.. traverse . getIdentifier
 
--- brittany-disable-next-binding
 runOtherSynth :: (Synthesize a) => Maybe a -> ModDecl -> Sh ()
 runOtherSynth (Just sim) m = runSynth sim m $ fromText [st|syn_#{toText sim}.v|]
-runOtherSynth Nothing m = writefile "syn_rtl.v" $ genSource m
+runOtherSynth Nothing    m = writefile "syn_rtl.v" $ genSource m
 
--- brittany-disable-next-binding
 runEquiv :: (Synthesize a, Synthesize b) => Yosys -> a -> Maybe b -> ModDecl -> Sh ()
 runEquiv yosys sim1 sim2 m = do
   writefile "top.v" . genSource . initMod $ makeTop 2 m
@@ -84,5 +82,9 @@ runEquiv yosys sim1 sim2 m = do
   runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
   runOtherSynth sim2 m
   run_ (yosysPath yosys) [checkFile]
-  where
-    checkFile = [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
+  where checkFile = [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
+
+-- | Generate @.il@ files for Yosys equivalence checking using the SAT solver.
+genIl :: (Synthesize a) => Yosys -> a -> ModDecl -> Sh ()
+genIl yosys sim m = do
+  return