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-rw-r--r--src/VeriFuzz/Verilog.hs4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index e6f8c54..a45922b 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -18,8 +18,6 @@ module VeriFuzz.Verilog
, GenVerilog(..)
, genSource
, getVerilog
- , Description(..)
- , getDescription
-- * Primitives
-- ** Identifier
, Identifier(..)
@@ -69,7 +67,6 @@ module VeriFuzz.Verilog
, exprFunc
, exprBody
, exprStr
- , traverseExpr
, ConstExpr(..)
, constNum
, Function(..)
@@ -90,7 +87,6 @@ module VeriFuzz.Verilog
, statements
, stmntBA
, stmntNBA
- , stmntCA
, stmntTask
, stmntSysTask
, stmntCondExpr