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-rw-r--r--src/VeriFuzz/Verilog.hs10
1 files changed, 1 insertions, 9 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index fdf2ac0..4d3b82c 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -14,12 +14,11 @@ module VeriFuzz.Verilog
( Verilog(..)
, parseVerilog
, procedural
+ , proceduralIO
, randomMod
, GenVerilog(..)
, genSource
, getVerilog
- , Description(..)
- , getDescription
-- * Primitives
-- ** Identifier
, Identifier(..)
@@ -69,8 +68,6 @@ module VeriFuzz.Verilog
, exprFunc
, exprBody
, exprStr
- , exprWithContext
- , traverseExpr
, ConstExpr(..)
, constNum
, Function(..)
@@ -91,7 +88,6 @@ module VeriFuzz.Verilog
, statements
, stmntBA
, stmntNBA
- , stmntCA
, stmntTask
, stmntSysTask
, stmntCondExpr
@@ -118,10 +114,6 @@ module VeriFuzz.Verilog
-- * Useful Lenses and Traversals
, getModule
, getSourceId
- -- * Arbitrary
- , Arb
- , arb
- , genPositive
)
where