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-rw-r--r--src/VeriFuzz/Verilog/AST.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 306366c..7a654fd 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -492,7 +492,7 @@ newtype Verilog = Verilog { getVerilog :: [ModDecl] }
data SourceInfo = SourceInfo { _infoTop :: {-# UNPACK #-} !Text
, _infoSrc :: !Verilog
}
- deriving (Eq, Show)
+ deriving (Eq, Ord, Data, Show)
$(makeLenses ''Expr)
$(makeLenses ''ConstExpr)