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-rw-r--r--src/VeriFuzz/Verilog/AST.hs3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index dd61f03..9db4999 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -514,8 +514,7 @@ modPortGen = QC.oneof
]
instance QC.Arbitrary ModDecl where
- arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary
- <*> QC.listOf1 modPortGen <*> QC.arbitrary
+ arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary <*> QC.listOf1 modPortGen <*> QC.arbitrary
-- | Description of the Verilog module.
newtype Description = Description { _getDescription :: ModDecl }