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-rw-r--r--src/VeriFuzz/Verilog/CodeGen.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 34194a6..1551c1d 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -91,7 +91,7 @@ genModuleItem (ModInst (Identifier i) (Identifier name) conn) =
i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n"
genModuleItem (Initial stat ) = "initial " <> genStmnt stat
genModuleItem (Always stat ) = "always " <> genStmnt stat
-genModuleItem (Decl dir port) = (maybe "" makePort dir) <> genPort port <> ";\n"
+genModuleItem (Decl dir port) = maybe "" makePort dir <> genPort port <> ";\n"
where makePort = (<> " ") . genPortDir
-- | Generate continuous assignment