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-rw-r--r--src/VeriFuzz/Verilog/CodeGen.hs2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 58b1d16..0b7f422 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -155,6 +155,8 @@ genEvent :: Event -> Text
genEvent (EId i ) = "@(" <> i ^. getIdentifier <> ")"
genEvent (EExpr expr) = "@(" <> genExpr expr <> ")"
genEvent EAll = "@*"
+genEvent (EPosEdge i) = "@(posedge " <> i ^. getIdentifier <> ")"
+genEvent (ENegEdge i) = "@(negedge " <> i ^. getIdentifier <> ")"
-- | Generates verilog code for a 'Delay'.
genDelay :: Delay -> Text