diff options
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index f20d959..2531519 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -55,7 +55,7 @@ moduleDecl (ModDecl i outP inP items ps) = <> ports <> ";\n" <> modI - <> "endmodule\n" + <> "endmodule\n\n" where ports | null outP && null inP = "" | otherwise = "(" <> comma (modPort <$> outIn) <> ")" |