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Diffstat (limited to 'src/VeriFuzz/Verilog/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index bc40de5..828224f 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -464,7 +464,7 @@ moduleDef top = do ^.. traverse . portSize let clock = Port Wire False 1 "clk" - let yport = Port Wire False size "y" + let yport = Port Wire False 1 "y" let comb = combineAssigns_ yport local return . declareMod local |