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-rw-r--r--src/VeriFuzz/Verilog/Gen.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 96a90f9..f4c49be 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -459,7 +459,7 @@ calcRange ps i (Range l r) = eval l - eval r + 1
moduleDef :: Maybe Identifier -> StateGen ModDecl
moduleDef top = do
name <- moduleName top
- portList <- some $ nextPort Wire
+ portList <- Hog.list (Hog.linear 4 10) $ nextPort Wire
mi <- Hog.list (Hog.linear 4 100) modItem
ps <- many parameter
context <- get