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-rw-r--r--src/VeriFuzz/Verilog/Helpers.hs3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs
index 90a5de4..554b8ba 100644
--- a/src/VeriFuzz/Verilog/Helpers.hs
+++ b/src/VeriFuzz/Verilog/Helpers.hs
@@ -14,7 +14,6 @@ module VeriFuzz.Verilog.Helpers where
import Control.Lens
import Data.Text (Text)
-import qualified Data.Text
import VeriFuzz.Verilog.AST
regDecl :: Identifier -> ModItem
@@ -69,4 +68,4 @@ defaultPort :: Identifier -> Port
defaultPort = Port Wire 1
portToExpr :: Port -> Expr
-portToExpr (Port _ _ id) = Id id
+portToExpr (Port _ _ i) = Id i