1 files changed, 13 insertions, 12 deletions
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index 5999a31..63072b1 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -16,7 +16,7 @@ module VeriFuzz.Verilog.Internal
     , emptyMod
     , setModName
     , addModPort
-    , addDescription
+    , addModDecl
     , testBench
     , addTestBench
     , defaultPort
@@ -33,14 +33,14 @@ import           Data.Text            (Text)
 import           VeriFuzz.Verilog.AST
 
 regDecl :: Identifier -> ModItem
-regDecl = Decl Nothing . Port Reg False 1
+regDecl i = Decl Nothing (Port Reg False 0 1 i) Nothing
 
 wireDecl :: Identifier -> ModItem
-wireDecl = Decl Nothing . Port Wire False 1
+wireDecl i = Decl Nothing (Port Wire False 0 1 i) Nothing
 
 -- | Create an empty module.
 emptyMod :: ModDecl
-emptyMod = ModDecl "" [] [] []
+emptyMod = ModDecl "" [] [] [] []
 
 -- | Set a module name for a module declaration.
 setModName :: Text -> ModDecl -> ModDecl
@@ -50,8 +50,8 @@ setModName str = modId .~ Identifier str
 addModPort :: Port -> ModDecl -> ModDecl
 addModPort port = modInPorts %~ (:) port
 
-addDescription :: Description -> Verilog -> Verilog
-addDescription desc = getVerilog %~ (:) desc
+addModDecl :: ModDecl -> Verilog -> Verilog
+addModDecl desc = getVerilog %~ (:) desc
 
 testBench :: ModDecl
 testBench = ModDecl
@@ -76,24 +76,25 @@ testBench = ModDecl
     -- , SysTaskEnable $ Task "finish" []
         ]
     ]
+    []
 
 addTestBench :: Verilog -> Verilog
-addTestBench = addDescription $ Description testBench
+addTestBench = addModDecl testBench
 
 defaultPort :: Identifier -> Port
-defaultPort = Port Wire False 1
+defaultPort = Port Wire False 0 1
 
 portToExpr :: Port -> Expr
-portToExpr (Port _ _ _ i) = Id i
+portToExpr (Port _ _ _ _ i) = Id i
 
 modName :: ModDecl -> Text
 modName = view $ modId . getIdentifier
 
 yPort :: Identifier -> Port
-yPort = Port Wire False 90
+yPort = Port Wire False 0 90
 
 wire :: Int -> Identifier -> Port
-wire = Port Wire False
+wire = Port Wire False 0
 
 reg :: Int -> Identifier -> Port
-reg = Port Reg False
+reg = Port Reg False 0