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-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 3f0ae83..66f3c37 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -49,6 +49,7 @@ import VeriFuzz.Circuit.Internal
import VeriFuzz.Internal
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.BitVec
+import VeriFuzz.Verilog.CodeGen
import VeriFuzz.Verilog.Internal
class Mutate a where
@@ -146,6 +147,9 @@ instance Mutate a => Mutate [a] where
instance Mutate a => Mutate (Maybe a) where
mutExpr f a = mutExpr f <$> a
+instance Mutate a => Mutate (GenVerilog a) where
+ mutExpr f (GenVerilog a) = GenVerilog $ mutExpr f a
+
-- | Return if the 'Identifier' is in a 'ModDecl'.
inPort :: Identifier -> ModDecl -> Bool
inPort i m = inInput