diff options
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index e7b4874..35e0458 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -118,9 +118,9 @@ allVars m = -- -- >>> render $ instantiateMod m main -- module main; --- wire [(3'h4):(1'h0)] y; --- reg [(3'h4):(1'h0)] x; --- m m1(y, x); +-- wire [(3'h4):(1'h0)] y; +-- reg [(3'h4):(1'h0)] x; +-- m m1(y, x); -- endmodule -- <BLANKLINE> -- <BLANKLINE> @@ -181,8 +181,8 @@ filterChar t ids = -- -- >>> GenVerilog $ initMod m -- module m(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- <BLANKLINE> |