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-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index dea5a66..eddb93a 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -139,10 +139,10 @@ makeIdFrom a i =
-- modules to instantiate.
makeTop :: Int -> ModDecl -> ModDecl
makeTop i m =
- ModDecl (m ^. moduleId) ys (m ^. modInPorts) modItems
+ ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt
where
ys = Port Wire 90 . (flip makeIdFrom) "y" <$> [1..i]
- modItems = instantiateMod_ . modN <$> [1..i]
+ modIt = instantiateMod_ . modN <$> [1..i]
modN n = m
& moduleId %~ makeIdFrom n
& modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")]