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-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 9f22faa..3052598 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -135,6 +135,6 @@ makeIdFrom a i = (i <>) . Identifier . ("_" <>) $ showT a
makeTop :: Int -> ModDecl -> ModDecl
makeTop i m = ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt
where
- ys = Port Wire 90 . (flip makeIdFrom) "y" <$> [1 .. i]
+ ys = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i]
modIt = instantiateMod_ . modN <$> [1 .. i]
modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")]