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-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 7b93633..e7b4874 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -123,6 +123,7 @@ allVars m =
-- m m1(y, x);
-- endmodule
-- <BLANKLINE>
+-- <BLANKLINE>
instantiateMod :: ModDecl -> ModDecl -> ModDecl
instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
where
@@ -184,6 +185,7 @@ filterChar t ids =
-- input wire [(3'h4):(1'h0)] x;
-- endmodule
-- <BLANKLINE>
+-- <BLANKLINE>
initMod :: ModDecl -> ModDecl
initMod m = m & modItems %~ ((out ++ inp) ++)
where