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Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 32f0833..dea5a66 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -119,7 +119,7 @@ instantiateMod_ m = -- | Initialise all the inputs and outputs to a module. -- --- >>> render $ initMod mod +-- >>> render $ initMod m -- module m(y, x); -- output wire [4:0] y; -- input wire [4:0] x; |