1 files changed, 6 insertions, 8 deletions
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index a072ce8..518bcb9 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -106,7 +106,7 @@ systemFunc s = satisfy' matchId
 parseFunction :: Parser Function
 parseFunction =
     systemFunc "$unsigned"
-        $>  UnSignedFunc
+        $>  UnsignedFunc
         <|> systemFunc "$signed"
         $>  SignedFunc
 
@@ -259,7 +259,7 @@ parseNetDecl pd = do
     range <- option 1 parseRange
     name  <- identifier
     tok' SymSemi
-    return . Decl pd . Port t sign range $ name
+    return $ Decl pd (Port t sign 0 range name) Nothing
     where type_ = tok KWWire $> Wire <|> tok KWReg $> Reg
 
 parsePortDir :: Parser PortDir
@@ -281,8 +281,8 @@ parseModList :: Parser [Identifier]
 parseModList = list <|> return [] where list = parens $ commaSep identifier
 
 filterDecl :: PortDir -> ModItem -> Bool
-filterDecl p (Decl (Just p') _) = p == p'
-filterDecl _ _                  = False
+filterDecl p (Decl (Just p') _ _) = p == p'
+filterDecl _ _                    = False
 
 modPorts :: PortDir -> [ModItem] -> [Port]
 modPorts p mis = filter (filterDecl p) mis ^.. traverse . declPort
@@ -298,14 +298,12 @@ parseModDecl = do
                      (modPorts PortOut modItem)
                      (modPorts PortIn modItem)
                      modItem
-
-parseDescription :: Parser Description
-parseDescription = Description <$> parseModDecl
+                     []
 
 -- | Parses a 'String' into 'Verilog' by skipping any beginning whitespace
 -- and then parsing multiple Verilog source.
 parseVerilogSrc :: Parser Verilog
-parseVerilogSrc = Verilog <$> many parseDescription
+parseVerilogSrc = Verilog <$> many parseModDecl
 
 -- | Parse a 'String' containing verilog code. The parser currently only supports
 -- the subset of Verilog that is being generated randomly.