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-rw-r--r--src/VeriFuzz/Verilog/Preprocess.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/VeriFuzz/Verilog/Preprocess.hs
index c783ac5..c30252b 100644
--- a/src/VeriFuzz/Verilog/Preprocess.hs
+++ b/src/VeriFuzz/Verilog/Preprocess.hs
@@ -1,5 +1,5 @@
{-|
-Module : VeriFuzz.Verilog.Preprocess
+Module : VeriSmith.Verilog.Preprocess
Description : Simple preprocessor for `define and comments.
Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz
License : GPL-3
@@ -14,7 +14,7 @@ The code is from https://github.com/tomahawkins/verilog.
Edits to the original code are warning fixes and formatting changes.
-}
-module VeriFuzz.Verilog.Preprocess
+module VeriSmith.Verilog.Preprocess
( uncomment
, preprocess
)