diff options
Diffstat (limited to 'src/VeriFuzz/Verilog')
-rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 18 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 14 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Helpers.hs | 2 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 4 |
4 files changed, 15 insertions, 23 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 9db4999..b3754ec 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -107,17 +107,13 @@ module VeriFuzz.Verilog.AST ) where -import Control.Lens ( makeLenses - , makePrisms - ) -import Control.Monad ( replicateM ) -import Data.String ( IsString - , fromString - ) -import Data.Text ( Text ) -import qualified Data.Text as T -import Data.Traversable ( sequenceA ) -import qualified Test.QuickCheck as QC +import Control.Lens (makeLenses, makePrisms) +import Control.Monad (replicateM) +import Data.String (IsString, fromString) +import Data.Text (Text) +import qualified Data.Text as T +import Data.Traversable (sequenceA) +import qualified Test.QuickCheck as QC positiveArb :: (QC.Arbitrary a, Ord a, Num a) => QC.Gen a positiveArb = QC.suchThat QC.arbitrary (> 0) diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 1551c1d..956472f 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -15,14 +15,12 @@ This module generates the code from the Verilog AST defined in module VeriFuzz.Verilog.CodeGen where -import Control.Lens ( view - , (^.) - ) -import Data.Foldable ( fold ) -import Data.Text ( Text ) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Numeric ( showHex ) +import Control.Lens (view, (^.)) +import Data.Foldable (fold) +import Data.Text (Text) +import qualified Data.Text as T +import qualified Data.Text.IO as T +import Numeric (showHex) import VeriFuzz.Verilog.AST -- | 'Source' class which determines that source code is able to be generated diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs index f910924..4771329 100644 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ b/src/VeriFuzz/Verilog/Helpers.hs @@ -13,7 +13,7 @@ Defaults and common functions. module VeriFuzz.Verilog.Helpers where import Control.Lens -import Data.Text ( Text ) +import Data.Text (Text) import VeriFuzz.Verilog.AST regDecl :: Identifier -> ModItem diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 3052598..82d3db9 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -14,9 +14,7 @@ more random patterns, such as nesting wires instead of creating new ones. module VeriFuzz.Verilog.Mutate where import Control.Lens -import Data.Maybe ( catMaybes - , fromMaybe - ) +import Data.Maybe (catMaybes, fromMaybe) import VeriFuzz.Internal.Gen import VeriFuzz.Internal.Shared import VeriFuzz.Verilog.AST |